1. Field of the Invention
The present invention relates to semiconductor device manufacturing and, more specifically, to a method of forming a barrier metal in a semiconductor device.
2. Discussion of the Related Art
Generally, a line width is still decreasing according to a highly increasing degree of integration in semiconductor devices. A microscopic line of a semiconductor device raises line resistance and delays a signal transfer. A single layer line structure has been replaced by a multi-layer line structure to solve the signal transfer delay problem.
Yet, as a distance between the lines in the multi-layer line structure is shortened, parasitic capacitance between the lines of the same layer increases to worsen the signal transfer delay in a semiconductor device. Specifically, in the case of a line having a microscopic line width, the signal transfer delay attributed to the parasitic capacitance of the line considerably affects the operational characteristics of the semiconductor device. To lower the parasitic capacitance between lines, a thickness of the line is lowered and an insulating interlayer is thickened. Hence, the line is formed of a line material having low specific resistance and the insulating interlayer is formed of a material having a low dielectric constant. For this, Cu is recommended as the line material and various materials are proposed as the material of the insulating interlayer. Yet, in case of Cu, dry etching has difficulty due to etch byproducts usually having a low vapor pressure.
To overcome such a problem, a via hole or a via hole and trench are formed in an insulating interlayer, the via or the via and trench are filled up with Cu, and planarization is then carried out. This is called a damascene or dual damascene process.
FIGS. 1A to 1E are cross-sectional diagrams for explaining a dual damascene process by ‘via first’ according to a related art.
Referring to FIG. 1A, a first insulating interlayer 102 is deposited on a semiconductor substrate 101 previously provided with a lower line and the like.
An etch-stop layer 103 is formed on the first insulating interlayer 102 using silicon nitride or the like.
And, a second insulating interlayer 104 having a low dielectric constant is deposited on the etch-stop layer 103.
Photoresist is coated on the second insulating interlayer 104 and is then selectively patterned to form a first photoresist pattern 105 exposing the second insulating interlayer 104 corresponding to a via hole area.
Referring to FIG. 1B, the exposed second insulating interlayer 104 is etched using the first photoresist pattern 105 as an etch mask. If the etch-stop layer 103 is exposed, the etch process keeps being carried out on the exposed etch-stop layer 103 and the first insulating interlayer 102 to complete a via hole 106.
Referring to FIG. 1C, after the first photoresist pattern has been removed, photoresist is coated over the substrate 101 including the second insulating interlayer 104. Exposure and development are selectively carried out on the photoresist to form a second photoresist pattern 107 exposing the second insulating interlayer 104 corresponding to a trench area.
Referring to FIG. 1D, the exposed second insulating interlayer 104 is etched using the second photoresist layer 107 as an etch mask to form a trench 108.
Referring to FIG. 1E, after the second photoresist pattern has been removed, a barrier metal layer 109 is formed to a prescribed thickness on insides of the via hole and trench.
Subsequently, a metal layer 110, e.g., a copper layer, is formed to fill up the via hole and trench.
The Cu metal layer 110 and the barrier metal layer 109 are planarized until the second insulating interlayer 104 is exposed to form a plug and upper metal line within the via hole and trench. Thus, the related art dual damascene process is completed.
Yet, in the related art semiconductor device structure, the barrier metal layer that is different from the metal lines is inserted between the upper and lower metal lines, thereby raising the resistance of the semiconductor device.
To overcome the raised resistance problem, a method according to another related art is proposed as follows.
First of all, a barrier metal layer is deposited in a via hole and trench. And, the barrier metal layer contacting with a lower metal line is then etched by plasma dry etch to expose the lower metal line.
However, the method according to another related art needs the additional etch step, thereby having difficulty in process reproducibility and optimal process condition setup.
And, the method according to another related art has difficulty in raising efficiency due to an increasing overall process time.
Moreover, in the method according to another related art, the structure in the vicinity of the barrier metal layer is damaged by plasma to lower device reliability.